Sangheon Lee

Orcid: 0000-0002-1491-0625

Affiliations:

Kwangwoon University, Seoul, South Korea

According to our database¹, Sangheon Lee authored at least 5 papers between 2023 and 2025.

Collaborative distances:

Dijkstra number² of six.
Erdős number³ of five.

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Bibliography

2025

Bayesian Learning-Enhanced Embedded Memory Design With Automated Circuit Variant Generation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025

Simultaneous Optimization of Various-Sized SRAM Instances Through Machine Learning-Driven Transistor Sizing and Leafcell Circuit Pool Construction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025

2024

Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory.

[BibT_eX]

[DOI]

Sangheon Lee

Gwanwoo Park

Hanwool Jeong

Sensors, 2024

2023

Cross-Coupled nFET Preamplifier for Low Voltage SRAM.

[BibT_eX]

[DOI]

Sangheon Lee

Jaehyun Park

Hanwool Jeong

IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM.

[BibT_eX]

[DOI]

Jaehyun Park

Sangheon Lee

Hanwool Jeong

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Sangheon Lee

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