Satinderjit Singh

According to our database1, Satinderjit Singh authored at least 3 papers between 2017 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Self-Timed Shaper Circuit for Wide Memories in Advanced CMOS Technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017


  Loading...