Satvik Maurya

According to our database, Satvik Maurya authored at least 13 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A Case for Elastic Quantum Error Correction Decoders.

Satvik Maurya, Abtin Molavi, Aws Albarghouthi, Swamit Tannu

Proceedings of the 21st European Conference on Computer Systems, 2026

PropHunt: Automated Optimization of Quantum Syndrome Measurement Circuits.

Joshua Viszlai, Satvik Maurya, Swamit Tannu, Margaret Martonosi, Frederic T. Chong

Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

2025

Enabling Fast and Accurate Neutral Atom Readout through Image Denoising.

Chaithanya Naik Mude, Linipun Phuttitarn, Satvik Maurya, Kunal Sinha, Mark Saffman, Swamit Tannu

CoRR, October, 2025

Synchronization for Fault-Tolerant Quantum Computers.

Satvik Maurya, Swamit Tannu

Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

decoder-bench: Benchmarking Decoders for Quantum Error Correction.

Satvik Maurya, Joshua Viszlai, Nithin Raveendran, Poulami Das, Swamit Tannu

Proceedings of the IEEE International Symposium on Workload Characterization, 2025

Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout.

Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

Managing Classical Processing Requirements for Quantum Error Correction.

Satvik Maurya, Swamit Tannu

CoRR, 2024

Enabling Leakage Reduction via Fast and High-Fidelity Qutrit Readout.

Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu

CoRR, 2024

Understanding Side-Channel Vulnerabilities in Superconducting Qubit Readout Architectures.

Satvik Maurya, Chaithanya Naik Mude, Benjamin Lienhard, Swamit Tannu

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024

2023

Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures.

Satvik Maurya, Chaithanya Naik Mude, William D. Oliver, Benjamin Lienhard, Swamit S. Tannu

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022

Hardware Efficient Neural Network Assisted Qubit Readout.

Satvik Maurya, Chaithanya Naik Mude, William D. Oliver, Benjamin Lienhard, Swamit S. Tannu

CoRR, 2022

COMPAQT: Compressed Waveform Memory Architecture for Scalable Qubit Control.

Satvik Maurya, Swamit S. Tannu

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2019

Hardware/Software Co-Design of a High-Speed Othello Solver.

Pranav Gangwar, Satvik Maurya, Shubham Garg, Sakshi Goyal, Aditya S. Kumar, Preyesh Dalmia, Neeta Pandey

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019