Satyanarayana Muddasani

According to our database, Satyanarayana Muddasani authored at least 3 papers between 2020 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2022

A Digital Frequency Locked Loop With Minimum Computation Overhead for Heavily Distorted Single-Phase Grid Systems.

Satyanarayana Muddasani, A. V. Ravi Teja

IEEE Trans. Instrum. Meas., 2022

2021

CORDIC based Orthogonal Signal Generation with In-loop Moving Average Filter for Single Phase PLL Systems.

Satyanarayana Muddasani, A. V. Ravi Teja

Proceedings of the IECON 2021, 2021

2020

Orthogonal Signal Generation based PLL using Arbitrary Order Exact Differentiator with Inherent Disturbance Rejection for Single Phase Systems.

Satyanarayana Muddasani, A. V. Ravi Teja

Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020