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Savvas G. Chamberlain

According to our database1, Savvas G. Chamberlain authored at least 6 papers between 1980 and 1995.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Awards

IEEE Fellow

IEEE Fellow 1991, "For contributions in CCD imagers and MOSFET's.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

1995
An Architecture for Integrated Reliability Simulators Using Analog Hardware Description Languages.
[BibTeX]
[DOI]
S. M. GadelRab
,
James A. Barby
,
Savvas G. Chamberlain
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1992
A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors.
[BibTeX]
[DOI]
John R. F. McMacken
,
Savvas G. Chamberlain
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991
Buried-channel MOSFET model for SPICE.
[BibTeX]
[DOI]
Michael J. Van der Tol
,
Savvas G. Chamberlain
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1989
CHORD: a modular semiconductor device simulation development tool incorporating external network models.
[BibTeX]
[DOI]
John R. F. McMacken
,
Savvas G. Chamberlain
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1984
Foreword.
[BibTeX]
[DOI]
Constantine N. Anagnostopoulos
,
Savvas G. Chamberlain
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1980
Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications.
[BibTeX]
[DOI]
Robert J. Inkol
,
Savvas G. Chamberlain
IEEE Trans. Computers, 1980


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