Scot W. Hornick

According to our database, Scot W. Hornick authored at least 7 papers between 1959 and 1991.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

1991

Deterministic P-RAM Simulation with Constant Redundancy

Scot W. Hornick, Franco P. Preparata

Inf. Comput., May, 1991

Optimal VLSI architectures for multidimensional DFT (preliminary version).

Gianfranco Bilardi, Scot W. Hornick, Majid Sarrafzadeh

SIGARCH Comput. Archit. News, 1991

1990

Searching on a Tape.

Scot W. Hornick, Sanjeev R. Maddila, Ernst P. Mücke, Harald Rosenberger, Steven Skiena, Ioannis G. Tollis

IEEE Trans. Computers, 1990

1989

The mesh of trees architecture for parallel computation

Scot W. Hornick

PhD thesis, 1989

Optimal VLSI Architectures for Multidimensional DFT.

Gianfranco Bilardi, Scot W. Hornick, Majid Sarrafzadeh

Proceedings of the ACM Symposium on Parallel Algorithms and Architectures, 1989

1987

On Problem Transformability in VLSI.

Scot W. Hornick, Majid Sarrafzadeh

Algorithmica, 1987

1959

IBM 709 Tape Matrix Compiler.

Scot W. Hornick

Commun. ACM, 1959