Se-Hyeon Kang
According to our database1,
Se-Hyeon Kang
authored at least 8 papers
between 2001 and 2007.
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Bibliography
2007
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2005
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Loosely coupled memory-based decoding architecture for low density parity check codes.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Memory-based low density parity check code decoder architecture using loosely coupled two data-flows.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001