Seied Zaniar Hoseini

According to our database1, Seied Zaniar Hoseini authored at least 9 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Current Feedback Instrumentation Amplifier With Built-In Differential Electrode Offset Cancellation Loop for ECG/EEG Sensing Frontend.
IEEE Trans. Instrum. Meas., 2021

2020
Design of an 8-bit time-mode cyclic ADC based on macro modeling.
Int. J. Circuit Theory Appl., 2020

2018
Compact Time-Mode SAR ADC With Capacitor Flipping Bit-Cycling Operation.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
2-Channel Electroencephalography Sensor Frontend for Portable Health Condition Monitoring Applications.
J. Low Power Electron., 2017

2015
An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications.
J. Circuits Syst. Comput., 2015

An area efficient 10-bit time mode hybrid DAC with current settling error compensation.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2014
Macro Modeling Approach for Semi-digital Smart Integrated Circuits.
Proceedings of the Frontier and Innovation in Future Computing and Communications, 2014

2013
An 8-bit 500kS/s semi-digital cyclic ADC with time-mode residue voltage generation.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2011
Design and Implementation of a Modified 1.5v High Speed Fuzzy Controller in Switched-Cap Technique.
Proceedings of the Artificial Intelligence and Computational Intelligence, 2011


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