Sergey G. Mosin

Orcid: 0000-0003-1389-2602

According to our database1, Sergey G. Mosin authored at least 17 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Bibliography

2020
An Accuracy Improvement of the Neuromorphic Functional Models by Using the Parallel ANN Architecture.
Proceedings of the IEEE East-West Design & Test Symposium, 2020

2018
Analogue Integrated Circuits Design-for-Testability Flow Oriented onto OBIST Strategy.
Inf. Technol. Control., 2018

Technique for Teaching Parallel Programming via Solving a Computational Electrodynamics Problems.
Proceedings of the Supercomputing, 2018

Entropy-based method of reducing the training set dimension at constructing a neuromorphic fault dictionary for analog and mixed-signal ICs.
Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018

A technique to aggregate classes of analog fault diagnostic data based on association rule mining.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

A Model of LoRaWAN Communication in Class A for Design Automation of Wireless Sensor Networks Based on the IoT Paradigm.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017
The State-of-the-Art Trends in Education Strategy for Sustainable Development of the High Performance Computing Ecosystem.
Proceedings of the Supercomputing, 2017

Automated simulation of faults in analog circuits based on parallel paradigm.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2015
A Technique of Analog Circuits Testing and Diagnosis Based on Neuromorphic Classifier.
Proceedings of the Advances in Signal Processing and Intelligent Recognition Systems, 2015

An approach to construction the neuromorphic classifier for analog fault testing and diagnosis.
Proceedings of the 4th Mediterranean Conference on Embedded Computing, 2015

Quality improvement of analog circuits fault diagnosis based on ANN using clusterization as preprocessing.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Test program generation for mixed-signal integrated circuits based on automata network.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

An automated technique for design of custom Network-on-Chip topologies.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2013
Design-for-testability automation of mixed-signal integrated circuits.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Methodology to design-for-testability automation for mixed-signal integrated circuits.
Proceedings of the East-West Design & Test Symposium, 2013

2011
A Built-in Self-Test Circuitry Based on Reconfiguration for Analog and Mixed-Signal IC.
Inf. Technol. Control., 2011

2010
A technique of optimal built-in self-test circuitries generation.
Proceedings of the 2010 East-West Design & Test Symposium, 2010


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