Shan Huang
Orcid: 0009-0005-2012-8540Affiliations:
- Shanghai Jiao Tong University, Shanghai, China
According to our database1,
Shan Huang authored at least 11 papers
between 2024 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2026
MARCA-v2: Mamba Accelerator With Complementary State-Space Model Sparsity and Reconfigurable Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2026
CoRR, February, 2026
2025
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2025
DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale.
Proceedings of the Thirteenth International Conference on Learning Representations, 2025
DyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node Partitioning, Low-Degree Sparsity, and Asynchronous Sub-Batch.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
ViDA: Video Diffusion Transformer Acceleration with Differential Approximation and Adaptive Dataflow.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
CoRR, 2024
Fast and Efficient 2-bit LLM Inference on GPU: 2/4/16-bit in a Weight Matrix with Asynchronous Dequantization.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024