# Shashi Kiran Chilappagari

According to our database

Collaborative distances:

^{1}, Shashi Kiran Chilappagari authored at least 26 papers between 2006 and 2012.Collaborative distances:

## Timeline

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## Bibliography

2012

IEEE Trans. Inf. Theory, 2012

2011

An Efficient Instanton Search Algorithm for LP Decoding of LDPC Codes Over the BSC.

IEEE Trans. Inf. Theory, 2011

2010

Error correction capability of column-weight-three LDPC codes under the Gallager A algorithm-Part II.

IEEE Trans. Inf. Theory, 2010

On trapping sets and guaranteed error correction capability of LDPC codes and GLDPC codes.

IEEE Trans. Inf. Theory, 2010

CoRR, 2010

Proceedings of the 2010 IEEE Information Theory Workshop, 2010

Proceedings of the Information Theory and Applications Workshop, 2010

Multilevel decoders surpassing belief propagation on the binary symmetric channel.

Proceedings of the IEEE International Symposium on Information Theory, 2010

Worst configurations (instantons) for Compressed Sensing over reals: A channel coding approach.

Proceedings of the IEEE International Symposium on Information Theory, 2010

2009

IEEE Trans. Inf. Theory, 2009

Instanton-based techniques for analysis and reduction of error floors of LDPC codes.

IEEE J. Sel. Areas Commun., 2009

Proceedings of the IEEE International Symposium on Information Theory, 2009

Two-bit message passing decoders for LDPC codes over the binary symmetric channel.

Proceedings of the IEEE International Symposium on Information Theory, 2009

2008

PhD thesis, 2008

Eliminating Trapping Sets in Low-Density Parity-Check Codes by Using Tanner Graph Covers.

IEEE Trans. Inf. Theory, 2008

Low-Density Parity-Check Codes Which Can Correct Three Errors Under Iterative Decoding

CoRR, 2008

Provably Efficient Instanton Search Algorithm for LP decoding of LDPC codes over the BSC

CoRR, 2008

CoRR, 2008

Proceedings of the 2008 IEEE Information Theory Workshop, 2008

Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008

2007

An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes.

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

CoRR, 2007

Proceedings of the IEEE International Symposium on Information Theory, 2007

2006

Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006

Proceedings of IEEE International Conference on Communications, 2006

Construction of Memory Circuits Using Unreliable Components Based on Low-Density Parity-Check Codes.

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006