Shenggang Dong

Orcid: 0000-0002-4530-5065

According to our database1, Shenggang Dong authored at least 5 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
A 430GHz CMOS Concurrent Transceiver Pixel Array for High Angular Resolution Reflection-Mode Active Imaging.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver.
IEEE J. Solid State Circuits, 2021

2020
315-GHz Self-Synchronizing Minimum Shift Keying Receiver in 65-nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Wideband 180-GHz Phase-Lacked-Loop Based MSK Receiver.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2018


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