Shenjian Zhang

According to our database, Shenjian Zhang authored at least 4 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things.

Shenjian Zhang, Chun Zhao, Yuxin Guan, Kai Tang, Junyan Li, Rui Li, Yun Fang, Hao Gao

Proceedings of the 16th IEEE Latin America Symposium on Circuits and Systems, 2025

Synaptic Thin-Film Transistor Model based on Behavioral Simulation.

Rui Li, Shenjian Zhang, Junyan Li, Yechen Lin, Changlin Qian, Yuxin Guan, Chun Zhao

Proceedings of the 16th IEEE Latin America Symposium on Circuits and Systems, 2025

A PVT-Insensitive 7-Bit Coarse-Fine Ratio-Metric Digital-to-Time Converter for Fractional-N Phase-Locked Loops in 65-nm CMOS.

Shenjian Zhang, Chenming Zhang, Hao Luo, Shengtao Yi, Xuewei Ding, Zhirui Zong

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2021

A Multi-Layered Air-Gap Transmission Line Design for CMOS-Compatible Millimeter-Wave ICs.

Shenjian Zhang, Sang Lam

Proceedings of the International Conference on IC Design and Technology, 2021