Sherif M. Sharroush

Orcid: 0000-0001-7911-2571

According to our database1, Sherif M. Sharroush authored at least 16 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Proposed time-mode wide fan-in NAND and NOR gates.
Int. J. Circuit Theory Appl., July, 2023

2020
Inverter-based voltage-controlled and programmable comparators.
Int. J. Circuit Theory Appl., 2020

An MTCMOS Subthreshold-Leakage Reduction Algorithm.
Proceedings of the 2nd Novel Intelligent and Leading Emerging Sciences Conference, 2020

Optimum Sizing of the Sleep Transistor in MTCMOS Technology.
Proceedings of the 2nd Novel Intelligent and Leading Emerging Sciences Conference, 2020

2019
A predischarged bitline 1T-1C DRAM readout scheme.
Microelectron. J., 2019

Design of the CMOS inverter-based amplifier: A quantitative approach.
Int. J. Circuit Theory Appl., 2019

A Novel Current-Domain DRAM Readout Scheme.
Proceedings of the 31st International Conference on Microelectronics, 2019

2018
Time-Domain Readout of 1T-1C DRAM Cells.
J. Circuits Syst. Comput., 2018

2017
A voltage-controlled ring oscillator based on an FGMOS transistor.
Microelectron. J., 2017

2016
Performance optimization of 1T-1C DRAMs: A quantitative study.
Microelectron. J., 2016

2015
An alternative to CMOS stacks based on a floating-gate transistor.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A novel self-referenced ferroelectric-memory readout scheme.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Reading DRAM cells using two properly designed cascaded inverters.
Elektrotech. Informationstechnik, 2014

2013
Low-power and high-speed DRAM readout scheme.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Dynamic random-access memories without sense amplifiers.
Elektrotech. Informationstechnik, 2012

2007
Increasing the Sense Margin of 1T-1C Ferroelectric Random-Access Memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


  Loading...