Shiyuan Huang

Orcid: 0000-0002-8086-6802

Affiliations:
  • Shanghai Jiao Tong University, Shanghai, China


According to our database1, Shiyuan Huang authored at least 12 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Attack and Defense: Enhancing Robustness of Binary Hyper-Dimensional Computing.
ACM Trans. Archit. Code Optim., September, 2025

SpMMPlu-Pro: An Enhanced Compiler Plug-In for Efficient SpMM and Sparsity Propagation Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization.
ACM Trans. Design Autom. Electr. Syst., 2025

FATE: Boosting the Performance of Hyper-Dimensional Computing Intelligence with Flexible Numerical DAta TypE.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

TAIL: Exploiting Temporal Asynchronous Execution for Efficient Spiking Neural Networks with Inter-Layer Parallelism.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

Exploiting Differential-Based Data Encoding for Enhanced Query Efficiency.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
COMPASS: SRAM-Based Computing-in-Memory SNN Accelerator with Adaptive Spike Speculation.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

LowPASS: A Low power PIM-based accelerator with Speculative Scheme for SNNs.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024


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