Shreyas Deshmukh

According to our database, Shreyas Deshmukh authored at least 5 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Band to Band Tunneling-Based Low Power and Low Area Tunable Spike Delay Element.

Abhishek A. Kadam, Shreyas Deshmukh, Laxmeesha Somappa, Maryam Shojaei Baghini, Udayan Ganguly

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

Area Efficient Multi-Memristor Bit Cell Design for Resistive Processing Unit-Based Neural Network Training.

Gaurav R, Ujwal Uttarwar, Shreyas Deshmukh, Jayatika Sakhuja, Kunal Randad, Samarth Agarwal, Akshata Koshti, Anmol Biswas, Udayan Ganguly

Proceedings of the 22nd Non-Volatile Memory Technology Symposium, 2024

Resistive Processing Unit-based On-chip ANN Training with Digital Memory.

Shreyas Deshmukh, Shubham Patil, Anmol Biswas, Vivek Saraswat, Abhishek Kadam, Ajay Kumar Singh, Laxmeesha Somappa, Maryam Shojaei Baghini, Udayan Ganguly

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Enhanced regularization for on-chip training using analog and temporary memory weights.

Raghav Singhal, Vivek Saraswat, Shreyas Deshmukh, Sreenivas Subramoney, Laxmeesha Somappa, Maryam Shojaei Baghini, Udayan Ganguly

Neural Networks, August, 2023

ANN Inference enabled by Variability Mitigation using 2T-1R Bit Cell-based Design Space Analysis.

Shreyas Deshmukh, Vivek Saraswat, Venkatesh Gopinath, Rajesh Nair, Laxmeesha Somappa, Maryam Shojaei Baghini, Udayan Ganguly

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023