Ajay Kumar Singh

Orcid: 0000-0002-6170-1340

Affiliations:
  • Multimedia University, Melaka, Malaysia


According to our database1, Ajay Kumar Singh authored at least 37 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Online presence:

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Bibliography

2024
Online teaching in Indian higher education institutions during the pandemic time.
Educ. Inf. Technol., March, 2024

2023
Development of a new task scheduling in cloud computing.
Int. J. Syst. Assur. Eng. Manag., December, 2023

'3D-QSAR-based, pharmacophore modelling, virtual screening, and molecular docking studies for identification of hypoxia-inducible factor-1 inhibitor with potential bioactivity.
Comput. Biol. Medicine, November, 2023

A Compact and Ultra-Low-Power Low-Pass Filter Based on Band-to-Band Tunneling Effect.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Ultrasound-Based Ovarian Cysts Detection with Improved Machine-Learning Techniques and Stage Classification Using Enhanced Classifiers.
SN Comput. Sci., September, 2023

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read-Write Assist (DARWA) Technique for Low-Power Applications.
Sensors, 2023

Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.
CoRR, 2023

Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron.
CoRR, 2023

Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing.
CoRR, 2023

Real-world Performance Estimation of Liquid State Machines for Spoken Digit Classification.
Proceedings of the International Joint Conference on Neural Networks, 2023

Multi Objective Optimization Based Land Cover Classification Using NSGA-II.
Proceedings of the 6th International Conference on Contemporary Computing and Informatics, 2023

Implementation of ABC & WOA-Based Security Defense Mechanism for Distributed Denial of Service Attacks.
Proceedings of the 6th International Conference on Contemporary Computing and Informatics, 2023

2022
Quantum Tunneling Based Ultra-Compact and Energy Efficient Spiking Neuron Enables Hardware SNN.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Valuable survey on scheduling algorithms in the cloud with various publications.
Int. J. Syst. Assur. Eng. Manag., 2022

Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021
Deep Hybrid Summarizer with Reinforced Sentence Selection.
Proceedings of the 25th Pacific Asia Conference on Information Systems, 2021

OBD - II based Intelligent Vehicular Diagnostic System using IoT.
Proceedings of the International Semantic Intelligence Conference 2021 (ISIC 2021), 2021

2020
A Portable System With 0.1-ppm RMSE Resolution for 1-10 MHz Resonant MEMS Frequency Measurement.
IEEE Trans. Instrum. Meas., 2020

Frequency Estimation for Resonant MEMS Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Estimation of Functional Connectivity Modulations During Task Engagement and Their Neurovascular Underpinnings Through Hemodynamic Reorganization Method.
Brain Connect., 2019

2018
Design of power efficient stable 1-bit full adder circuit.
IEICE Electron. Express, 2018

2016
Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption.
J. Low Power Electron., 2016

2015
ANPR Indian system using surveillance cameras.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015

2014
A data aware 9T static random access memory cell for low power consumption and improved stability.
Int. J. Circuit Theory Appl., 2014

Low-power reliable SRAM cell for write/read operation.
IEICE Electron. Express, 2014

2013
Low Power and High Performance Single-Ended Sense amplifier.
J. Circuits Syst. Comput., 2013

Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis.
Int. J. Circuit Theory Appl., 2013

2011
Low-power fast (LPF) SRAM cell for write/read operation.
IEICE Electron. Express, 2011

2010
A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after considering quantum confinement parameter.
Microelectron. J., 2010

Novel Eight-Transistor SRAM cell for write power reduction.
IEICE Electron. Express, 2010

2009
Low Power, Low Latency, High Throughput 16-Bit CSA Adder Using Nonclocked Pass-Transistor Logic.
J. Circuits Syst. Comput., 2009

Vector quantized signal dependant Delta-Sigma modulator based high performance three-phase switching converter.
IEICE Electron. Express, 2009

Delta-Sigma Modulator based multiplier.
IEICE Electron. Express, 2009

Analog Multiplier with High Accuracy.
Proceedings of the First International Conference on Computational Intelligence, 2009

2008
Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell.
Microelectron. J., 2008

Highly stable Delta-Sigma Modulator for industrial applications.
IEICE Electron. Express, 2008

2004
TCP-ADA: TCP with adaptive delayed acknowledgement for mobile ad hoc networks.
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004


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