Ajay Kumar Singh

  • Multimedia University, Melaka, Malaysia

According to our database1, Ajay Kumar Singh authored at least 23 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.



In proceedings 
PhD thesis 


Online presence:

On csauthors.net:


Quantum Tunneling Based Ultra-Compact and Energy Efficient Spiking Neuron Enables Hardware SNN.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Valuable survey on scheduling algorithms in the cloud with various publications.
Int. J. Syst. Assur. Eng. Manag., 2022

Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Deep Hybrid Summarizer with Reinforced Sentence Selection.
Proceedings of the 25th Pacific Asia Conference on Information Systems, 2021

OBD - II based Intelligent Vehicular Diagnostic System using IoT.
Proceedings of the International Semantic Intelligence Conference 2021 (ISIC 2021), 2021

Estimation of Functional Connectivity Modulations During Task Engagement and Their Neurovascular Underpinnings Through Hemodynamic Reorganization Method.
Brain Connect., 2019

Design of power efficient stable 1-bit full adder circuit.
IEICE Electron. Express, 2018

Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption.
J. Low Power Electron., 2016

ANPR Indian system using surveillance cameras.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015

A data aware 9T static random access memory cell for low power consumption and improved stability.
Int. J. Circuit Theory Appl., 2014

Low-power reliable SRAM cell for write/read operation.
IEICE Electron. Express, 2014

Low Power and High Performance Single-Ended Sense amplifier.
J. Circuits Syst. Comput., 2013

Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis.
Int. J. Circuit Theory Appl., 2013

Low-power fast (LPF) SRAM cell for write/read operation.
IEICE Electron. Express, 2011

A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after considering quantum confinement parameter.
Microelectron. J., 2010

Novel Eight-Transistor SRAM cell for write power reduction.
IEICE Electron. Express, 2010

Low Power, Low Latency, High Throughput 16-Bit CSA Adder Using Nonclocked Pass-Transistor Logic.
J. Circuits Syst. Comput., 2009

Vector quantized signal dependant Delta-Sigma modulator based high performance three-phase switching converter.
IEICE Electron. Express, 2009

Delta-Sigma Modulator based multiplier.
IEICE Electron. Express, 2009

Analog Multiplier with High Accuracy.
Proceedings of the First International Conference on Computational Intelligence, 2009

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell.
Microelectron. J., 2008

Highly stable Delta-Sigma Modulator for industrial applications.
IEICE Electron. Express, 2008

TCP-ADA: TCP with adaptive delayed acknowledgement for mobile ad hoc networks.
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004