Ajay Kumar Singh
Affiliations:- Multimedia University, Melaka, Malaysia
According to our database1,
Ajay Kumar Singh
authored at least 23 papers
between 2004 and 2022.
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Bibliography
2022
Quantum Tunneling Based Ultra-Compact and Energy Efficient Spiking Neuron Enables Hardware SNN.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Int. J. Syst. Assur. Eng. Manag., 2022
Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
2021
Proceedings of the 25th Pacific Asia Conference on Information Systems, 2021
Proceedings of the International Semantic Intelligence Conference 2021 (ISIC 2021), 2021
2019
Estimation of Functional Connectivity Modulations During Task Engagement and Their Neurovascular Underpinnings Through Hemodynamic Reorganization Method.
Brain Connect., 2019
2018
IEICE Electron. Express, 2018
2016
Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption.
J. Low Power Electron., 2016
2015
Proceedings of the Eighth International Conference on Contemporary Computing, 2015
2014
A data aware 9T static random access memory cell for low power consumption and improved stability.
Int. J. Circuit Theory Appl., 2014
2013
J. Circuits Syst. Comput., 2013
Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis.
Int. J. Circuit Theory Appl., 2013
2011
IEICE Electron. Express, 2011
2010
A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after considering quantum confinement parameter.
Microelectron. J., 2010
IEICE Electron. Express, 2010
2009
Low Power, Low Latency, High Throughput 16-Bit CSA Adder Using Nonclocked Pass-Transistor Logic.
J. Circuits Syst. Comput., 2009
Vector quantized signal dependant Delta-Sigma modulator based high performance three-phase switching converter.
IEICE Electron. Express, 2009
Proceedings of the First International Conference on Computational Intelligence, 2009
2008
Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell.
Microelectron. J., 2008
IEICE Electron. Express, 2008
2004
Proceedings of the 2004 IEEE Wireless Communications and Networking Conference , 2004