Shrinidhi Udupi

Orcid: 0000-0002-3683-0888

According to our database1, Shrinidhi Udupi authored at least 4 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2019
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2017
Dynamic Power Optimization based on Formal Property Checking of Operations.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

2016
Properties first? a new design methodology for hardware, and its perspectives in safety analysis.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2013
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013


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