Simon J. Bale

Orcid: 0000-0002-3361-5648

According to our database1, Simon J. Bale authored at least 24 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Multi-objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow.
IET Comput. Digit. Tech., 2023

2022
A Multi-objective Evolutionary Approach for Efficient Kernel Size and Shape for CNN.
Proceedings of the International Joint Conference on Neural Networks, 2022

2021
Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Multi-objective Digital Design Optimisation via Improved Drive Granularity Standard Cells.
CoRR, 2021

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow.
CoRR, 2021

Adaptive Integer Quantisation for Convolutional Neural Networks through Evolutionary Algorithms.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021

Implementation of Reduced Precision Integer Epigenetic Networks in Hardware.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021

2019
Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs.
IET Comput. Digit. Tech., 2019

Approximate Multiply-Accumulate Array for Convolutional Neural Networks on FPGA.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

2018
Instrumenting Parametric Physical Layout for Multi-objective Optimisation.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2018

2017
Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device.
IEEE Trans. Computers, 2017

An evolutionary approach to runtime variability mapping and mitigation on a multi-reconfigurable architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Variability mapping at runtime using the PAnDA multi-reconfigurable architecture.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2015
Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration.
IET Comput. Digit. Tech., 2015

Two-phase multiobjective genetic algorithm for constrained circuit clustering on FPGAs.
Proceedings of the IEEE Congress on Evolutionary Computation, 2015

2014
Circuit design optimisation using a modified genetic algorithm and device layout motifs.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

Multiobjective genetic algorithm for routability-driven circuit clustering on FPGAs.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

Evolving hierarchical low disruption fault tolerance strategies for a novel programmable device.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

Optimising ring oscillator frequency on a novel FPGA device via partial reconfiguration.
Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

Two step evolution strategy for device motif BSIM model parameter extraction.
Proceedings of the IEEE Congress on Evolutionary Computation, 2014

A hierarchical fault tolerant system on the PAnDA device with low disruption.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations.
IEEE Trans. Computers, 2013

Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations.
Proceedings of the 2013 IEEE International Conference on Evolvable Systems, 2013

Overcoming faults using evolution on the PAnDA architecture.
Proceedings of the IEEE Congress on Evolutionary Computation, 2013


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