Siva Ramakrishna Pillutla

According to our database, Siva Ramakrishna Pillutla authored at least 7 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2024

A Novel Approach to Implement a 4-Bit Vedic Multiplier Using Reversible Techniques.

Aruru Sai Kumar, Siva Ramakrishna Pillutla, T. Venkanna Babu, Akanksha Nitin Kabra, Poluri Kavyasree, Maidamshetty Rahul

Proceedings of the 15th International Conference on Computing Communication and Networking Technologies, 2024

2022

An Efficient two Dimensional Mapping of External Surroundings for Robotics and Drones.

Siva Ramakrishna Pillutla, N. Neelima, Aruru Sai Kumar, Bandi Narasimha Rao, Namgiri Suresh

Proceedings of the 13th International Conference on Computing Communication and Networking Technologies, 2022

2021

Low-latency area-efficient systolic bit-parallel <i>GF</i>(2m) multiplier for a narrow class of trinomials.

Siva Ramakrishna Pillutla, Lakshmi Boppana

Microelectron. J., 2021

Low-complexity bit-serial sequential polynomial basis finite field GF(2m) Montgomery multipliers.

Siva Ramakrishna Pillutla, Lakshmi Boppana

Microprocess. Microsystems, 2021

2020

Area-efficient low-latency polynomial basis finite field GF(2^<i>m</i>) systolic multiplier for a class of trinomials.

Siva Ramakrishna Pillutla, Lakshmi Boppana

Microelectron. J., 2020

High-throughput area-delay-efficient systolic multiplier over GF(2^<i>m</i>) for a class of trinomials.

Siva Ramakrishna Pillutla, Lakshmi Boppana

Microprocess. Microsystems, 2020

2019

A high-throughput fully digit-serial polynomial basis finite field GF(2^m) multiplier for IoT applications.

Siva Ramakrishna Pillutla, Lakshmi Boppana

Proceedings of the TENCON 2019, 2019