Sreeja Rajendran

According to our database, Sreeja Rajendran authored at least 5 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Enhancing SRAM Array Security Through Transmission Gate-Based Logic Obfuscation.

Bhavin Bhavani, Anupam Mathur, Sreeja Rajendran, Vinay Palaparthy, Yash Agrawal

Proceedings of the 33rd IEEE Asian Test Symposium, 2024

2022

A Novel Algorithm for Hardware Trojan Detection Through Reverse Engineering.

Sreeja Rajendran, Mary Lourde Regeena

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020

Sensitivity analysis of testability parameters for secure IC design.

Sreeja Rajendran, Mary Lourde Regeena

IET Comput. Digit. Tech., 2020

2016

Ab-initio study on FinFETs and their application in loT aided robotics.

Sreeja Rajendran, R. Mary Lourde

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2015

Fin FETs and their Application as Load Switches in Micromechatronics.

Sreeja Rajendran, R. Mary Lourde

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015