Yash Agrawal

According to our database, Yash Agrawal authored at least 22 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Filtering-RRT for Autonomous Indoor Navigation.

Akshat Vikram Singh, Yash Agrawal, Rahul Gupta, Vivek Ashok Bohara

Proceedings of the 16th International Conference on COMmunication Systems & NETworkS, 2024

Real-Time Video PLC Using In-Painting.

Rajani Katiyar, Prasenjit Chakraborty, Ravi Surana, Ravishankar Holla, Sanka Sanjana, Sathvik Acharya, Sonia Singh B, Yash Agrawal

Proceedings of the 16th International Conference on COMmunication Systems & NETworkS, 2024

2023

iYogacare: Real-Time Yoga Recognition and Self-Correction for Smart Healthcare.

Abhishek Sharma, Yash Shah, Yash Agrawal, Prateek Jain

IEEE Consumer Electron. Mag., July, 2023

ANROLA: Autonomous Navigation with ROS and Laser Odometry.

Akshat Vikram Singh, Yash Agrawal, Rahul Gupta, Abhishek Kumar, Vivek Ashok Bohara

Proceedings of the 15th International Conference on COMmunication Systems & NETworkS, 2023

ANROL: Autonomous Navigation based on ROS and Laser Odometry.

Akshat Vikram Singh, Yash Agrawal, Rahul Gupta, Abhishek Kumar, Vivek Ashok Bohara

Proceedings of the 15th International Conference on COMmunication Systems & NETworkS, 2023

2022

Truncated Models for Probabilistic Weighted Retrieval.

Jiaul H. Paik, Yash Agrawal, Sahil Rishi, Vaishal Shah

ACM Trans. Inf. Syst., 2022

Real-time Recognition of Yoga Poses using computer Vision for Smart Health Care.

Abhishek Sharma, Yash Shah, Yash Agrawal, Prateek Jain

CoRR, 2022

End-to-end table structure recognition and extraction in heterogeneous documents.

Tejas Kashinath, Twisha Jain, Yash Agrawal, Tanvi Anand, Sanjay Singh

Appl. Soft Comput., 2022

2021

A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects.

Girish Kumar Mekala, Yash Agrawal, Vobulapuram Ramesh Kumar, Rajeevan Chandel

Microelectron. J., 2021

Hierarchical Model for Goal Guided Summarization of Annual Financial Reports.

Yash Agrawal, Vivek Anand, S. Arunachalam, Vasudeva Varma

Proceedings of the Companion of The Web Conference 2021, 2021

CNTFET Based Low Power Repeaters for On-Chip Interconnect System.

Takshashila Pathade, Yash Agrawal, Rutu Parekh, Girish Kumar Mekala

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design.

Yatin Kumar Gupta, Yash Agrawal, Rutu Parekh, Bakul Gohel

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Goal-Directed Extractive Summarization of Financial Reports.

Yash Agrawal, Vivek Anand, Manish Gupta, S. Arunachalam, Vasudeva Varma

Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021

2020

Design of prominent SET-based high performance computing system.

Rashmit Patel, Yash Agrawal, Rutu Parekh

IET Circuits Devices Syst., 2020

Predictive Staffing Model for Transit Security.

Yong Zheng, Shubham Madke, Vih Modeste Dogo, Yash Agrawal

Proceedings of the SIGITE '20: The 21st Annual Conference on Information Technology Education, 2020

2019

A Literature Review on Next Generation Graphene Interconnects.

Nikita Patel, Yash Agrawal

J. Circuits Syst. Comput., 2019

2018

A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects.

Yash Agrawal, Girish Kumar Mekala, Rajeevan Chandel

Circuits Syst. Signal Process., 2018

Cyberbullying Detection System with Multiple Server Configurations.

Rohit Pawar, Yash Agrawal, Akshay Joshi, Ranadheer Gorrepati, Rajeev R. Raje

Proceedings of the 2018 IEEE International Conference on Electro/Information Technology, 2018

2017

Modelling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects.

Girish Kumar Mekala, Yash Agrawal, Rajeevan Chandel

IET Circuits Devices Syst., 2017

Design and Optimization of Single Electron Transistor Based 4-Bit Arithmetic and Logic Unit at Room Temperature Operation.

Rathin K. Joshi, Rutu Parekh, Yash Agrawal

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2015

Timing and Stability Analysis of Carbon Nanotube Interconnects.

Girish Kumar Mekala, Rajeevan Chandel, Yash Agrawal

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Performance Analysis of Multilayer Graphene Nano-Ribbon in Current-Mode Signaling Interconnect System.

Yash Agrawal, Rajeevan Chandel, Girish Kumar Mekala

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015