Sreenivasulu Polineni

According to our database, Sreenivasulu Polineni authored at least 6 papers between 2018 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2021

A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications.

Sreenivasulu Polineni, S. Rekha, M. S. Bhat

IET Circuits Devices Syst., 2021

2020

A 0.3-V, 2.4-nW, and 100-Hz fourth-order LPF for ECG signal processing.

G. Hanumantha Rao, Sreenivasulu Polineni, S. Rekha, M. S. Bhat

Int. J. Circuit Theory Appl., 2020

A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique.

Sreenivasulu Polineni, M. S. Bhat, S. Rekha

Circuits Syst. Signal Process., 2020

2019

A 0.3 V, 56 dB DR, 100 Hz fourth order low-pass filter for ECG acquisition system.

Sreenivasulu Polineni, G. Hanumanta Rao, S. Rekha, M. S. Bhat

Microelectron. J., 2019

Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology.

Samarth Bonthala, Yashas Uppoor, Ashika Nayak, Sreenivasulu Polineni, M. S. Bhat

Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

2018

91dB Dynamic Range 9.5nW Low Pass Filter for Bio-Medical Applications.

M. K. Jayaram Reddy, Sreenivasulu Polineni, Laxminidhi Tonse

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018