Sudha Ellison Mathe

According to our database, Sudha Ellison Mathe authored at least 11 papers between 2017 and 2025.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2025

A comprehensive review on hardware implementations of lattice-based cryptographic schemes.

Shaik Ahmadunnisa, Sudha Ellison Mathe

J. Syst. Archit., 2025

FPGA based high speed parallel modular polynomial multiplier for lattice based cryptosystems.

Mamatha Bandaru, Sudha Ellison Mathe

Comput. Electr. Eng., 2025

2024

CNC: A lightweight architecture for Binary Ring-LWE based PQC.

Shaik Ahmadunnisa, Sudha Ellison Mathe

Microprocess. Microsystems, 2024

<i>x</i>²<i>DL</i>: A high throughput architecture for binary-ring-learning-with-error-based post quantum cryptography schemes.

Shaik Ahmadunnisa, Sudha Ellison Mathe

IET Quantum Commun., 2024

A comprehensive review on applications of Raspberry Pi.

Sudha Ellison Mathe, Hari Kishan Kondaveeti, Suseela Vappangi, Sunny Dayal Vanambathina, Nandeesh Kumar Kumaravelu

Comput. Sci. Rev., 2024

Evaluation of hardware and software implementations for NIST finalist and fourth-round post-quantum cryptography KEMs.

Mamatha Bandaru, Sudha Ellison Mathe, Chirawat Wattanapanich

Comput. Electr. Eng., 2024

Multi-LFSR Architectures for BRLWE-Based Post Quantum Cryptography.

Shaik Ahmadunnisa, Sudha Ellison Mathe

IEEE Access, 2024

2021

A systematic literature review on prototyping with Arduino: Applications, challenges, advantages, and limitations.

Hari Kishan Kondaveeti, Nandeesh Kumar Kumaravelu, Sunny Dayal Vanambathina, Sudha Ellison Mathe, Suseela Vappangi

Comput. Sci. Rev., 2021

2018

Design and Implementation of a Novel Bit-Parallel Systolic Multiplier Over GF(2^<i>m</i>) for Irreducible Pentanomials.

Sudha Ellison Mathe, Lakshmi Boppana

J. Circuits Syst. Comput., 2018

Bit-parallel systolic multiplier over GF ( 2 m ) for irreducible trinomials with ASIC and FPGA implementations.

Sudha Ellison Mathe, Lakshmi Boppana

IET Circuits Devices Syst., 2018

2017

Design and Implementation of a Sequential Polynomial Basis Multiplier over GF(2m).

Sudha Ellison Mathe, Lakshmi Boppana

KSII Trans. Internet Inf. Syst., 2017