Sumanta Pyne
Orcid: 0000-0002-7860-4002
According to our database1,
Sumanta Pyne
authored at least 28 papers
between 2011 and 2023.
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Bibliography
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
J. Circuits Syst. Comput., November, 2023
Microprocess. Microsystems, April, 2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
Microprocess. Microsystems, October, 2022
Droplet Routing Based on Double Deep Q-Network Algorithm for Digital Microfluidic Biochips.
J. Circuits Syst. Comput., 2022
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2021
Invasive weed optimization based scheduling for digital microfluidic biochip operations.
Integr., 2021
A hybrid artificial bee colony algorithm for scheduling of digital microfluidic biochip operations.
Concurr. Comput. Pract. Exp., 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Reinforcement Learning based Droplet Routing Algorithm for Digital Microfluidic Biochips.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
Scheduling of dual supercapacitor for longer battery lifetime in safety-critical embedded systems with power gating.
IET Comput. Digit. Tech., 2019
Scheduling of Dual Supercapacitor for Longer Battery Lifetime in Systems with Power Gating.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
ABC-GNX: A Hybrid Algorithm for Scheduling of Digital Microfluidic Biochip Operations.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019
Heterogeneous Earliest Finish Time based Scheduling for Digital Microfluidic Biochips.
Proceedings of the 12th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2019), 2019
2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018
Scheduling of Hybrid Battery-Supercapacitor Control Instructions for Longevity in Systems with Power Gating.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2015
Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence.
J. Low Power Electron., 2015
J. Low Power Electron., 2015
2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
2013
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
2012
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques.
J. Low Power Electron., 2012
2011
Wirel. Networks, 2011