Sundarrajan Rangachari

Orcid: 0000-0003-2170-3285

According to our database1, Sundarrajan Rangachari authored at least 6 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2020
Energy Reduction in Turbo Decoding through Dynamically Varying Bit-Widths.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017
Scenario-Aware Dynamic Power Reduction Using Bias Addition.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2014
Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
Scalable low power digital filter architectures for varying input dynamic range.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2006
A noise-estimation algorithm for highly non-stationary environments.
Speech Commun., 2006

2004
A noise estimation algorithm with rapid adaptation for highly nonstationary environments.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004


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