Sung-Mo Kang

According to our database1, Sung-Mo Kang authored at least 179 papers between 1982 and 2019.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2001, "For outstanding contributions to computer-aided design for performance and reliability of CMOS VLSI and optoelectronic circuits and systems for high performance computing and communications.".

IEEE Fellow

IEEE Fellow 1990, "For technical contributions to and leadership in the development of computer-aided design of very-large-scale integrated (VLSI) circuits and systems.".

Timeline

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Article 
PhD thesis 
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On csauthors.net:

Bibliography

2019
Real Time Image Processing System for Detecting Infrastructure Damage: Crack.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2018
Shape and orientation control of moving formation in multi-agent systems without global reference frame.
Automatica, 2018

Shape and Orientation Control of Moving Formation with Local Measurements in Three-Dimensional Space.
Proceedings of the IEEE Conference on Control Technology and Applications, 2018

Disturbance Attenuation in Distance-Based Formation Control: A Linear Matrix Inequality Approach.
Proceedings of the IEEE Conference on Control Technology and Applications, 2018

2017
Distance-Based Cycle-Free Persistent Formation: Global Convergence and Experimental Test With a Group of Quadcopters.
IEEE Trans. Industrial Electronics, 2017

Global convergence of formation without global information in three-dimensional space.
Proceedings of the 11th Asian Control Conference, 2017

2016
Design and Realization of Distributed Adaptive Formation Control Law for Multi-Agent Systems With Moving Leader.
IEEE Trans. Industrial Electronics, 2016

RRAM-based TCAMs for pattern search.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices.
IEEE Trans. VLSI Syst., 2014

A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS.
J. Solid-State Circuits, 2014

Distance-based formation control with a single moving leader.
Proceedings of the American Control Conference, 2014

2013
Resistive Computing: Memristors-Enabled Signal Multiplication.
IEEE Trans. on Circuits and Systems, 2013

Sliding mode controller design for spacecraft with manipulator.
Proceedings of the 9th Asian Control Conference, 2013

2012
Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs.
Proceedings of the IEEE, 2012

Memristors: Devices, Models, and Applications [Scanning the Issue].
Proceedings of the IEEE, 2012

Fast settling frequency synthesizer with two-point channel control paths.
I. J. Circuit Theory and Applications, 2012

Memristive computing- multiplication and correlation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Maximizing power harvest in a distributed photovoltaic system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations.
IEEE Trans. on Circuits and Systems, 2011

Field Programmable Stateful Logic Array.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits.
J. Low Power Electronics, 2011

Complementary structure of memristive devices based passive memory arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Stateful logic pipeline architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices.
IEEE Trans. on Circuits and Systems, 2010

Compact Models for Memristors Based on Charge-Flux Constitutive Relationships.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

2009
A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs.
IEICE Electronic Express, 2009

New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design of a 6 bit 1.25 GS/s DAC for WPAN.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL.
IEEE Trans. on Circuits and Systems, 2007

Programmable High Speed Multi-Level Simultaneous Bidirectional I/O.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Temperature-Aware Placement for SOCs.
Proceedings of the IEEE, 2006

Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A 32-bit carry lookahead adder using dual-path all-N logic.
IEEE Trans. VLSI Syst., 2005

3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Message from the General Chair.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Energy-efficient skewed static logic with dual Vt: design and synthesis.
IEEE Trans. VLSI Syst., 2003

Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. VLSI Syst., 2003

Minimum delay optimization for domino circuits - a coupling-aware approach.
ACM Trans. Design Autom. Electr. Syst., 2003

Chip-level charged-device modeling and simulation in CMOS integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Elements of low power design for integrated systems.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Noise constrained transistor sizing and power optimization for dual Vst domino logic.
IEEE Trans. VLSI Syst., 2002

Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst., 2002

Domino logic synthesis based on implication graph.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Optimal Timing for Skew-Tolerant High-Speed Domino Logic.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

On-chip thermal engineering for peta-scale integration.
Proceedings of 2002 International Symposium on Physical Design, 2002

A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design limitations in deep sub-0.1µm CMOS SRAM.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain.
Proceedings of the 2002 Design, 2002

VeriCDF: a new verification methodology for charged device failures.
Proceedings of the 39th Design Automation Conference, 2002

Low-swing clock domino logic incorporating dual supply and dual threshold voltages.
Proceedings of the 39th Design Automation Conference, 2002

2001
Crosstalk noise minimization in domino logic design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

New current-mode sense amplifiers for high density DRAM and PIM architectures.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Trapezoid-to-simple polygon recomposition for resistance extraction.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Full chip ESD design rule checking.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

ESD design rule checker.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Energy-efficient skewed static logic design with dual Vt.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A low-power reduced swing single clock flip-flop.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Coupling-aware minimum delay optimization for domino logic circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Skew-tolerant high-speed (STHS) domino logic.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Noise constrained power optimization for dual VT domino logic.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Transistor sizing for reliable domino logic design in dual threshold voltage technologies.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Effective algorithms for cache-level compression.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
Proceedings of the 38th Design Automation Conference, 2001

2000
Cell-level placement for improving substrate thermal distribution.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A temperature-aware simulation environment for reliable ULSI chipdesign.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Interconnect thermal modeling for accurate simulation of circuittiming and reliability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Real-time prioritized call admission control in a base station scheduler.
Proceedings of the Third ACM International Workshop on Wireless Mobile Multimedia, 2000

Noise-aware power optimization for on-chip interconnect.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Detection and elimination of initial transient for accurate power analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

New high performance sub-1 V circuit technique with reduced standby current and robust data holding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An algorithm for automatic model-order reduction of nonlinear MEMS devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Technology independent arbitrary device extractor.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Compensation modeling for QoS support on a wireless network.
Proceedings of the Global Telecommunications Conference, 2000. GLOBECOM 2000, San Francisco, CA, USA, 27 November, 2000

Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction.
Proceedings of the 37th Conference on Design Automation, 2000

When bad things happen to good chips (panel session).
Proceedings of the 37th Conference on Design Automation, 2000

Domino logic synthesis minimizing crosstalk.
Proceedings of the 37th Conference on Design Automation, 2000

1999
ServerNet and ATM interconnects: Comparison for compressed video transmission.
Journal of Communications and Networks, 1999

Standard cell placement for even on-chip thermal distribution.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Interconnect thermal modeling for determining design limits on current density.
Proceedings of the 1999 International Symposium on Physical Design, 1999

CMOS Pass-gate No-race Charge-recycling Logic (CPNCL).
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Macrocell placement with temperature profile optimization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Temperature-driven power and timing analysis for CMOS ULSI circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Implication graph based domino logic synthesis.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An efficient method for hot-spot identification in ULSI circuits.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

No-Race Charge-Recycling Differential Logic (NCDL).
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

NMOS Energy Recovery Logic.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Logic Transformation for Low Power Synthesis.
Proceedings of the 1999 Design, 1999

Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Statistical estimation of average power dissipation using nonparametric techniques.
IEEE Trans. VLSI Syst., 1998

ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Matrix unit cell scheduler (MUCS) for input-buffered ATM switches.
IEEE Communications Letters, 1998

Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Layout Extraction and Verification Methodology CMOS I/O Circuits.
Proceedings of the 35th Conference on Design Automation, 1998

1997
iTEM: a temperature-dependent electromigration reliability diagnosis tool.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus.
IEEE Journal on Selected Areas in Communications, 1997

A sequential procedure for average power analysis of sequential circuits.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches.
Proceedings of the Proceedings IEEE INFOCOM '97, 1997

Performance Comparison of Video Transport over ATM and ServerNet Interconnects.
Proceedings of the International Conference on Multimedia Computing and Systems, 1997

Data Link Level Support for Handoff in Wireless ATM Network.
Proceedings of the 1997 IEEE International Conference on Communications: Towards the Knowledge Millennium, 1997

Statistical Estimation of Average Power Dissipation in Sequential Circuits.
Proceedings of the 34st Conference on Design Automation, 1997

An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design.
Proceedings of the 34st Conference on Design Automation, 1997

1996
A new triple-layer OTC channel router.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Determining accuracy bounds for simulation-based switching activity estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits.
Proceedings of the 1996 European Design and Test Conference, 1996

Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects.
Proceedings of the 33st Conference on Design Automation, 1996

iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Efficient approximation of the time domain response of lossy coupled transmission line trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Worst-case analysis and optimization of VLSI circuit performances.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

An algorithm for functional verification of digital ECL circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Incremental Node Extraction Algorithms for Incremental Layout System.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Chip-Level Thermal Simulator to Predict VLSI Chip Temperature.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Estimating Node Voltages in Bipolar Circuits Using Linear Programming.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A timing-driven data path layout synthesis with integer programming.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

An empirical model for accurate estimation of routing delay in FPGAs.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Convexity-based algorithms for design centering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Genetic Algorithm Based Design Optimization Of CMOS VLSI Circuits.
Proceedings of the Parallel Problem Solving from Nature, 1994

High Performance CMOS Macromodule Layout Synthesis.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Fast timing simulation of transient faults in digital circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
ILLIADS: a fast timing and reliability simulator for digital MOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

High-Performance MCM Routing.
IEEE Design & Test of Computers, 1993

Feasible Region Approximation Using Convex Polytopes.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Functional Verification of ECL Circuits Including Voltage Regulators.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Fast Approximation of the Transient Response of Lossy Transmision Line Trees.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Analytic transient solution of general MOS circuit primitives.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

New algorithms for circuit simulation of device breakdown.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Detailed layer assignment for MCM routing.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1991
An accurate analytical delay model for BiCMOS driver circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

A new circuit optimization technique for high performance CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

iCOACH: A circuit optimization aid for CMOS high-performance circuits.
Integration, 1991

Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models.
I. J. Circuit Theory and Applications, 1991

New Simulation Methods for MOS VLSI Timing and Reliability.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach.
Proceedings of the 28th Design Automation Conference, 1991

1990
A global delay model for domino cmos circuits with application to transistor sizing.
I. J. Circuit Theory and Applications, 1990

An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
An efficient method for parametric yield optimization of MOS integrated circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A custom cell generation system for double-metal CMOS technology.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
iEDISON: an interactive statistical design tool for MOS VLSI circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

An efficient method for circuit sensitivity calculation using piecewise linear waveform models.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

An Efficient Approach to Gate Matrix Layout.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

1983
Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1983

1982
Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design.
Proceedings of the 19th Design Automation Conference, 1982


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