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Surendra Sagar

Orcid: 0000-0003-0044-2565

Affiliations:
  • Indian Institute of Technology Dhanbad, India


According to our database1, Surendra Sagar authored at least 4 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Resistorless Floating/Grounded Memristor Emulator Model With Electronic Tunability.
[BibTeX]
[DOI]
Surendra Sagar
,
Rajeev Kumar Ranjan
,
Sung-Mo Kang
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

2021
Resistorless Memristor Emulator Using CFTA and Its Experimental Verification.
[BibTeX]
[DOI]
Sagar Surendra Prasad
,
Prashant Kumar
,
Rajeev Kumar Ranjan
IEEE Access, 2021

2019
Memristor Emulator Circuit Using Multiple-Output OTA and Its Experimental Results.
[BibTeX]
[DOI]
Rajeev Kumar Ranjan
,
Pankaj Kumar Sharma
,
Surendra Sagar
,
Niranjan Raj
,
Bharti Kumari
,
Fabian Khateb
J. Circuits Syst. Comput., 2019

High-frequency floating memristor emulator and its experimental results.
[BibTeX]
[DOI]
Rajeev Kumar Ranjan
,
Surendra Sagar
,
Subrato Roushan
,
Bharti Kumari
,
Nishtha Rani
,
Fabian Khateb
IET Circuits Devices Syst., 2019


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