Sureshchander

According to our database, Sureshchander authored at least 9 papers between 1968 and 1978.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1978

Comments on "Delayed Universal Logic Modules and Sequential Machine Synthesis".

Sureshchander

IEEE Trans. Computers, 1978

1975

Minimization of Switching Functions - A Fast Technique.

Sureshchander

IEEE Trans. Computers, 1975

1974

A New Representation of Sequential Machines for Determining All Incompatible Pairs.

Sureshchander, P. C. P. Bhatt

IEEE Trans. Computers, 1974

A Note on Q-Universal Logic Modules.

Sureshchander, P. C. P. Bhatt

IEEE Trans. Computers, 1974

An Algorithm for Testing Asummability of Boolean Functions.

Sureshchander

IEEE Trans. Computers, 1974

1973

Comments on "Decomposition Method of Determining Maximum Compatibles".

Sureshchander

IEEE Trans. Computers, 1973

1970

RST Flip-Flop Input Equations.

Sureshchander

IEEE Trans. Computers, 1970

Comments on "The Synthesis of Binary Sequence Detectors".

Sureshchander

IEEE Trans. Computers, 1970

1968

Comments on "RST Flip-Flop Input Equations".

Sureshchander

IEEE Trans. Computers, 1968