Surin Kittitornkun

J. Mobile Multimedia, 2021

2020

A MultiStack Parallel (MSP) Partition Algorithm Applied to Sorting.

[BibT_eX]

[DOI]

Apisit Rattanatranurak

J. Mobile Multimedia, 2020

2017

A Spatio-Temporal malware and country clustering algorithm: 2012 IIJ MITF case study.

[BibT_eX]

[DOI]

Int. J. Inf. Sec., 2017

2016

Parallel Partition and Merge QuickSort (PPMQSort) on Multicore CPUs.

[BibT_eX]

[DOI]

Ratthaslip Ranokphanuwat

J. Supercomput., 2016

2013

Time Zone Correlation Analysis of Malware/Bot Downloads.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2013

2012

Geographical Visualization of Malware Download for Anomaly Detection.

[BibT_eX]

[DOI]

Proceedings of the Seventh Asia Joint Conference on Information Security, 2012

2010

Massively Parallel Cuckoo Pattern Matching Applied for NIDS/NIPS.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009

PAMELA: Pattern Matching Engine with Limited-Time Update for NIDS/NIPS.

[BibT_eX]

[DOI]

Shigenori Tomiyama

IEICE Trans. Inf. Syst., 2009

2007

Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPS.

[BibT_eX]

[DOI]

Tran Ngoc Thinh

Shigenori Tomiyama

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS.

[BibT_eX]

[DOI]

Proceedings of the Managing Next Generation Networks and Services, 2007

2006

MT-ClustalW: multithreading multiple sequence alignment.

[BibT_eX]

[DOI]

Kridsadakorn Chaichoompu

Sissades Tongsima

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Manifold similarity search of DNA sequences with reconfigurable hardware.

[BibT_eX]

[DOI]

Shigenori Tomiyama

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2003

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Processor Array Synthesis from Shift-Variant Deep Nested Do Loops.

[BibT_eX]

[DOI]

J. Supercomput., 2003

Supersystolic arrays on large-scale FPGA structures.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001

Frame-level pipelined motion estimation array processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2001

Efficient Implementation of Nested-Loop Multimedia Algorithms.

[BibT_eX]

[DOI]