Surya Shankar Dan
According to our database1,
Surya Shankar Dan
authored at least 9 papers
between 2009 and 2025.
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Bibliography
2025
An Experimental Demonstration of Neuronal Somatic Behavior Using 2D SnS Memristive Switching Characteristics and its Equivalent Circuit for Spiking Neural Network.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025
2021
Double-gate line-tunneling field-effect transistor devices for superior analog performance.
Int. J. Circuit Theory Appl., 2021
2020
Microelectron. J., 2020
Integr., 2020
2019
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
2010
Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor- single electron transistor integrated circuits.
IET Circuits Devices Syst., 2010
2009
Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin Modeling.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009