Santanu Mahapatra

Orcid: 0000-0003-1112-8109

According to our database1, Santanu Mahapatra authored at least 16 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Massive Monte Carlo simulations-guided interpretable learning of two-dimensional Curie temperature.
Patterns, 2022

2020
First Principles Based Compact Model for 2D-Channel MOSFETs.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

2019
Insights on Anisotropic Dissipative Quantum Transport in n-Type Phosphorene MOSFET.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018
New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top Contact.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2016
Compact noise modelling for common double-gate metal-oxide-semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetry.
IET Circuits Devices Syst., 2016

2014
Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2010
Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor- single electron transistor integrated circuits.
IET Circuits Devices Syst., 2010

A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin Modeling.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008
Drive current boosting of n-type tunnel FET with strained SiGe layer at source.
Microelectron. J., 2008

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
Modeling and Analysis of Noise Margin in SET Logic.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2003
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
A SET quantizer circuit aiming at digital communication system.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Few electron devices: towards hybrid CMOS-SET integrated circuits.
Proceedings of the 39th Design Automation Conference, 2002


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