Sushmita Kadiyala Rao

According to our database, Sushmita Kadiyala Rao authored at least 8 papers between 2012 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Scalability study of PSANDE: Power supply analysis for noise and delay estimation.

Sushmita Kadiyala Rao, Bharath Shivashankar, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Transient current estimation using S3C (Standard cell current transient characterization).

Michael Skaggs, Sushmita Kadiyala Rao, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Estimation of dynamic current waveforms using pre-characterization of standard cells.

Bharath Shivashankar, Michael Skaggs, Sushmita Kadiyala Rao, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel

Proceedings of the 16th Latin-American Test Symposium, 2015

Post-layout estimation of side-channel power supply signatures.

Sushmita Kadiyala Rao, Deepak Krishnankutty, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

2014

Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay.

Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel

J. Electron. Test., 2014

2013

Scalable dynamic technique for accurately predicting power-supply noise and path delay.

Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Framework for dynamic estimation of power-supply noise and path delay.

Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Estimating Power Supply Noise and its impact on path delay.

Sushmita Kadiyala Rao, Chaitra Sathyanarayana, Ajay Kallianpur, Ryan W. Robucci, Chintan Patel

Proceedings of the 30th IEEE VLSI Test Symposium, 2012