T. Nakano

According to our database, T. Nakano authored at least 4 papers between 1985 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm² bit density with 3.2Gbps interface and 205MB/s program throughput.

Mario Sako, T. Nakajima, Fumihiro Kono, T. Nakano, Masaki Fujiu, Junji Musha, Dai Nakamura, Naoaki Kanagawa, Y. Shimizu, Kosuke Yanagidaira, Tetsuaki Utsumi, T. Kawano, Yoshikazu Hosomura, Hiroki Yabe, M. Kano, Hiroshi Sugawara, A. H. Sravan, K. Hayashi, Toshiyuki Kouchi, Y. Watanabe

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2016

State-of-the-art of plate forging in Japan.

Ken-ichi Mori, T. Nakano

Prod. Eng., 2016

2006

Wind tunnel testing of shear-stress measurement by liquid-crystal coating.

T. Nakano, Nobuyuki Fujisawa

J. Vis., 2006

1985

Test Pattern Considerations for Fault Tolerant High Density DRAM.

Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano

Proceedings of the Proceedings International Test Conference 1985, 1985