Takashi Kodera
According to our database1,
Takashi Kodera
authored at least 3 papers
between 2000 and 2002.
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Bibliography
2002
J. Syst. Archit., 2002
2000
Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000