Tamer A. Ali

According to our database1, Tamer A. Ali authored at least 17 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Diagonal Mode: A New Mode for Triboelectric Anogenerators Energy Harvesters.
Proceedings of the 2018 New Generation of CAS, 2018

A New CAD Tool for Energy Optimization of Diagonal Motion Mode of Attached Electrode Triboelectric Nanogenerators.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016

2014
Short paper: MPOT: 3D Mote Placement Optimization algorithms for WSNs.
Proceedings of the IEEE World Forum on Internet of Things, 2014

Short paper: MPOT: 3D Mote placement optimization tool for wireless sensor networks.
Proceedings of the IEEE World Forum on Internet of Things, 2014

A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding.
IEEE J. Solid State Circuits, 2013

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Design of a 100+ meter 12Gb/s/Lane Copper Cable Link Based on Clock-Forwarding.
PhD thesis, 2012

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.
IEEE J. Solid State Circuits, 2012

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding.
Proceedings of the Symposium on VLSI Circuits, 2012

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Clocking Links in Multi-chip Packages: A Case Study.
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010


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