Tejinder Singh Sandhu

According to our database, Tejinder Singh Sandhu authored at least 5 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs.

Yang Ge, Tejinder Singh Sandhu, Dmitri V. Truhachev, Kamal El-Sankary

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

2019

Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures.

Tejinder Singh Sandhu, Kamal El-Sankary

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Beyond Rail-to-Rail Compliant Current Sources for Mismatch-Insensitive Voltage-to-Time Conversion.

Tejinder Singh Sandhu, Kamal El-Sankary

IEEE Trans. Very Large Scale Integr. Syst., 2018

2016

A Mismatch-Insensitive Skew Compensation Architecture for Clock Synchronization in 3-D ICs.

Tejinder Singh Sandhu, Kamal El-Sankary

IEEE Trans. Very Large Scale Integr. Syst., 2016

2010

A Distortion-Compensated Charge Transfer Amplifier for a 1.66-MHz Cyclic Pipeline ADC.

Tejinder Singh Sandhu, Kamal El-Sankary, Ezz I. El-Masry

IEEE Trans. Circuits Syst. II Express Briefs, 2010