Thomas Lundqvist

Proceedings of the 3rd Workshop on Co-Scheduling of HPC Applications, 2018

2017

Flipping the Data Center Network: Increasing East-West Capacity Using Existing Hardware.

[BibT_eX]

[DOI]

H. Robert H. Andersson

Proceedings of the 42nd IEEE Conference on Local Computer Networks, 2017

Disallowing Same-program Co-schedules to Improve Efficiency in Quad-core Servers.

[BibT_eX]

[DOI]

Proceedings of the Joined Workshops COSH 2017 and VisorHPC 2017, 2017

Thing-to-thing electricity micro payments using blockchain technology.

[BibT_eX]

[DOI]

H. Robert H. Andersson

Proceedings of the Global Internet of Things Summit, 2017

2016

Initial Formulation of Why Disallowing Same Program Co-Schedules Improves Performance.

[BibT_eX]

[DOI]

Proceedings of the Co-Scheduling of HPC Applications [extended versions of all papers from COSH@HiPEAC 2016, 2016

Terrible Twins: A Simple Scheme to Avoid Bad Co-Schedules.

[BibT_eX]

[DOI]

Proceedings of the 1st COSH Workshop on Co-Scheduling of HPC Applications, 2016

2015

Addressing characterization methods for memory contention aware co-scheduling.

[BibT_eX]

[DOI]

J. Supercomput., 2015

2002

A WCET Analysis Method for Pipelined Microprocessors with Cache Memories.

[BibT_eX]

[DOI]

PhD thesis, 2002

1999

An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution.

[BibT_eX]

[DOI]

Real Time Syst., 1999

Timing Anomalies in Dynamically Scheduled Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Real-Time Systems Symposium, 1999

A Method to Improve the Estimated Worst-Case Performance of Data Caching.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Real-Time Computing and Applications Symposium (RTCSA '99), 1999

1998

Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques.

[BibT_eX]

[DOI]