Tianshuo Lu
Orcid: 0009-0005-9301-4130
According to our database1,
Tianshuo Lu authored at least 5 papers
between 2025 and 2026.
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Bibliography
2026
An efficient RISC-V processor with customized instruction set for sparse DNN acceleration on embedded system.
J. Syst. Archit., 2026
2025
ISRLUT: Integer-Only FHD Image Super-Resolution Based on Neural Lookup Table and Near-Memory Computing.
ACM Trans. Reconfigurable Technol. Syst., December, 2025
Optimizing Sparse Matrix Convolution on RISC-V Core: Custom Instructions for Embedded System.
ACM Trans. Embed. Comput. Syst., November, 2025
RV-ESMC: Efficient Sparse Matrix Convolution Processor based on RISC-V Custom instructions for Edge Platforms.
Proceedings of the 33rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2025
EVO-QNN: Efficient Mixed-Precision Quantization Inference on RISC-V-Based Edge Device.
Proceedings of the 33rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2025