Tobias Scheipel

According to our database, Tobias Scheipel authored at least 7 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems.

Tobias Scheipel, Florian Angermair, Marcel Baunach

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime.

Tobias Scheipel, Peter Brungs, Marcel Baunach

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020

papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software.

Tobias Scheipel, Marcel Baunach

Proceedings of the 9th International Conference on Sensor Networks, 2020

FPGA-Based Debugging with Dynamic SignalSelection at Run-Time.

Gernot Fiala, Tobias Scheipel, Werner Neuwirth, Marcel Baunach

Proceedings of the Combined Proceedings of the Workshops at Software Engineering 2020 Co-located with the German Software Engineering Conference 2020 (SE 2020), 2020

2018

Smart mobility of the future - a challenge for embedded automotive systems.

Marcel Baunach, Renata Martins Gomes, Maja Malenko, Fabian Mauroner, Leandro Batista Ribeiro, Tobias Scheipel

Elektrotech. Informationstechnik, 2018

2017

Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur.

Tobias Scheipel, Fabian Mauroner, Marcel Baunach

Proceedings of the Logistik und Echtzeit, 2017

System-Aware Performance Monitoring Unit for RISC-V Architectures.

Tobias Scheipel, Fabian Mauroner, Marcel Baunach

Proceedings of the Euromicro Conference on Digital System Design, 2017