Tomohiro Korikawa

According to our database, Tomohiro Korikawa authored at least 13 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Device Type Classification Based on Two-Stage Traffic Behavior Analysis.

Chikako Takasaki, Tomohiro Korikawa, Kyota Hattori, Hidenari Ohwada

IEICE Trans. Commun., January, 2024

2023

Recursive Router Metrics Prediction Using Machine Learning-Based Node Modeling for Network Digital Replica.

Kyota Hattori, Tomohiro Korikawa, Chikako Takasaki, Hidenari Oowada

IEEE Access, 2023

Traffic Behavior-based Device Type Classification.

Chikako Takasaki, Tomohiro Korikawa, Kyota Hattori, Hidenari Ohwada

Proceedings of the International Conference on Computing, Networking and Communications, 2023

Time-Topology Routing in 3D Networks.

Tomohiro Korikawa, Chikako Takasaki, Kyota Hattori, Hidenari Oowada

Proceedings of the International Conference on Computing, Networking and Communications, 2023

2022

Memory Network Architecture for Packet Processing in Functions Virtualization.

Tomohiro Korikawa, Eiji Oki

IEEE Trans. Netw. Serv. Manag., 2022

Network Digital Replica using Neural-Network-based Network Node Modeling.

Kyota Hattori, Tomohiro Korikawa, Chikako Takasaki, Hidenari Oowada, Masafumi Shimizu, Naoki Takaya

Proceedings of the 8th IEEE International Conference on Network Softwarization, 2022

Recursive Router Metrics Prediction Using ML-based Node Modeling for Network Digital Replica.

Kyota Hattori, Tomohiro Korikawa, Chikako Takasaki, Hidenari Oowada, Masafumi Shimizu

Proceedings of the IEEE Global Communications Conference, 2022

2021

Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM.

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki

IEICE Trans. Commun., 2021

2020

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM.

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki

IEEE Access, 2020

2019

Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis.

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki

IEEE Access, 2019

Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM.

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki

Proceedings of the 20th IEEE International Conference on High Performance Switching and Routing, 2019

2018

Carrier-Scale Packet Processing System Using Interleaved 3D-Stacked DRAM.

Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki

Proceedings of the 2018 IEEE International Conference on Communications, 2018

2017

Toward carrier-scale general-purpose node.

Tomohiro Korikawa, Akio Kawabata, Akeo Masuda

Proceedings of the 2017 International Conference on Computing, 2017