Tomoko Ogura Iwasaki

According to our database, Tomoko Ogura Iwasaki authored at least 3 papers between 2014 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.

Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi

IEEE J. Solid State Circuits, 2016

2015

Reliability enhancement of 1Xnm TLC for cold flash and millennium memories.

Senju Yamazaki, Shuhei Tanakamaru, Sakuya Suzuki, Tomoko Ogura Iwasaki, Shogo Hachiya, Ken Takeuchi

Proceedings of the Symposium on VLSI Circuits, 2015

2014

Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD.

Chao Sun, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi, Ken Takeuchi

IEEE Trans. Circuits Syst. I Regul. Pap., 2014