Tzung-Chin Chang

According to our database1, Tzung-Chin Chang authored at least 2 papers between 2004 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2005
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface.
IEEE J. Solid State Circuits, 2005

2004
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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