Ulrich Langmann

According to our database1, Ulrich Langmann authored at least 8 papers between 1991 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2008
A 22.3dB Voltage Gain 6.1dB NF 60GHz LNA in 65nm CMOS with Differential Output.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 90GHz 65nm CMOS Injection-Locked Frequency Divider.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Channel Equalization in HSDPA Receivers: Trade-Off between Performance and Complexity with a Variable Oversampling.
Proceedings of the 63rd IEEE Vehicular Technology Conference, 2006

2003
Excess loop delay effects in continuous-time quadrature bandpass sigma-delta modulators.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1999
Design of high speed bipolar Si/SiGe ICs for optical wide band communications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1991
Multi-Gb/s Silicon Bipolar Clock Recovery IC.
IEEE J. Sel. Areas Commun., 1991


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