Umakanta Nanda
Orcid: 0000-0003-4746-5297
According to our database1,
Umakanta Nanda
authored at least 11 papers
between 2012 and 2024.
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Bibliography
2024
Physics based model development of a double gate reverse T-shaped channel TFET including 1D and 2D band-to-band tunneling components.
Microelectron. J., February, 2024
Design of robust analog integrated circuit based on process corner performance variability minimization.
Integr., January, 2024
2023
Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions.
Microelectron. J., 2023
2022
Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction.
Microelectron. J., 2022
2020
A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance.
Microelectron. J., 2020
2018
A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate.
Microelectron. J., 2018
2017
Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios.
Microelectron. J., 2017
2016
A Novel Error Detection Strategy for a Low Power Low Noise All-Digital Phase-Locked Loop.
J. Low Power Electron., 2016
2014
Low Noise and Fast Locking Phase Locked Loop Using a Variable Delay Element in the Phase Frequency Detector.
J. Low Power Electron., 2014
A New Transmission Gate Cascode Current Mirror Charge Pump for Fast Locking Low Noise PLL.
Circuits Syst. Signal Process., 2014
2012
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012