Vacius Jusas

According to our database, Vacius Jusas authored at least 42 papers between 2001 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Implementation Framework for a Blockchain-Based Federated Learning Model for Classification Problems.

Zeba Mahmood, Vacius Jusas

Symmetry, 2021

2020

An Ontology Based on the Timeline of Log2timeline and Psort Using Abstraction Approach in Digital Forensics.

Sandeepak Bhandari, Vacius Jusas

Symmetry, 2020

An Abstraction Based Approach for Reconstruction of TimeLine in Digital Forensics.

Sandeepak Bhandari, Vacius Jusas

Symmetry, 2020

The Phases Based Approach for Regeneration of Timeline in Digital Forensics.

Sandeepak Bhandari, Vacius Jusas

Proceedings of the International Conference on INnovations in Intelligent SysTems and Applications, 2020

2019

Robust Backstepping Sliding Mode Control with L2-Gain Performance for Reference Input Wheel Slip Tracking of Vehicle.

Vacius Jusas, Jiaxu Zhang, Jing Li

Inf. Technol. Control., December, 2019

Classification of Motor Imagery Using Combination of Feature Extraction and Reduction Methods for Brain-Computer Interface.

Vacius Jusas, Sam Gilvine Samuvel

Inf. Technol. Control., 2019

Logical filter approach for early stage cyber-attack detection.

Vacius Jusas, Saulius Japertas, Tautvydas Baksys, Sandeepak Bhandari

Comput. Sci. Inf. Syst., 2019

2018

Development of a Modular Board for EEG Signal Acquisition.

Tomas Uktveris, Vacius Jusas

Sensors, 2018

Black box delay fault models for non-scan sequential circuits.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Liudas Motiejunas, Rimantas Seinauskas

Comput. Sci. Inf. Syst., 2018

2017

Methods and Tools of Digital Triage in Forensic Context: Survey and Future Directions.

Vacius Jusas, Darius Birvinskas, Elvar Gahramanov

Symmetry, 2017

Application of Convolutional Neural Networks to Four-Class Motor Imagery Classification Problem.

Tomas Uktveris, Vacius Jusas

Inf. Technol. Control., 2017

Methodology to investigate BitTorrent sync protocol.

Algimantas Venckauskas, Vacius Jusas, Kestutis Paulikas, Jevgenijus Toldinas

Comput. Sci. Inf. Syst., 2017

Software Engineering Competence Remote Evaluation Process Model.

Vacius Jusas, Joaquín Nicolás Ros, Boriss Misnevs

Balt. J. Mod. Comput., 2017

Convolutional Neural Networks for Four-Class Motor Imagery Data Classification.

Tomas Uktveris, Vacius Jusas

Proceedings of the Intelligent Distributed Computing XI - Proceedings of the 11th International Symposium on Intelligent Distributed Computing, 2017

2016

A Methodology and Tool for Investigation of Artifacts Left by the BitTorrent Client.

Algimantas Venckauskas, Vacius Jusas, Kestutis Paulikas, Jevgenijus Toldinas

Symmetry, 2016

2015

Investigation of Artifacts Left by BitTorrent Client on the Local Computer Operating under Windows 8.1.

Algimantas Venckauskas, Vacius Jusas, Kestutis Paulikas, Jevgenijus Toldinas

Inf. Technol. Control., 2015

Path delay test generation at functional level.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

IET Comput. Digit. Tech., 2015

Fast DCT algorithms for EEG data compression in embedded systems.

Darius Birvinskas, Vacius Jusas, Ignas Martisius, Robertas Damasevicius

Comput. Sci. Inf. Syst., 2015

Comparison of Feature Extraction Methods for EEG BCI Classification.

Tomas Uktveris, Vacius Jusas

Proceedings of the Information and Software Technologies - 21st International Conference, 2015

Energy Efficient Method for Motor Imagery Data Compression.

Darius Birvinskas, Vacius Jusas

Proceedings of the Information and Software Technologies - 21st International Conference, 2015

2014

Stimuli generation framework for testing multiple processes in VHDL.

Vacius Jusas, Tomas Neverdauskas

Inf. Technol. Control., 2014

Stimuli generator for testing processes in VHDL.

Vacius Jusas, Tomas Neverdauskas

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2013

Delay fault testing using partial multiple scan chains.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2013

Combining Software and Hardware Test Generation Methods to Verify VHDL Models.

Vacius Jusas, Tomas Neverdauskas

Inf. Technol. Control., 2013

Data compression of EEG signals for artificial neural network classification.

Darius Birvinskas, Vacius Jusas, Ignas Martisius, Robertas Damasevicius

Inf. Technol. Control., 2013

Functional delay test generation approach using a software prototype of the circuit.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Comput. Sci. Inf. Syst., 2013

Novel Method to Generate Tests for VHDL.

Vacius Jusas, Tomas Neverdauskas

Proceedings of the Information and Software Technologies - 19th International Conference, 2013

EEG Dataset Reduction and Classification Using Wave Atom Transform.

Ignas Martisius, Darius Birvinskas, Robertas Damasevicius, Vacius Jusas

Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2013, 2013

2012

Evaluation of testability enhancement using software prototype.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

IET Comput. Digit. Tech., 2012

FSM Based Functional Test Generation Framework for VHDL.

Vacius Jusas, Tomas Neverdauskas

Proceedings of the Information and Software Technologies - 18th International Conference, 2012

EEG Dataset Reduction and Feature Extraction Using Discrete Cosine Transform.

Darius Birvinskas, Vacius Jusas, Ignas Martisius, Robertas Damasevicius

Proceedings of the Sixth UKSim/AMSS European Symposium on Computer Modeling and Simulation, 2012

2011

Functional fault models for non-scan sequential circuits.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2011

2009

Functional delay test generation based on software prototype.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2009

2008

Test generation at the algorithm-level for gate-level fault coverage.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2008

Development of Functional Delay Tests.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Functional Test Generation Based on Combined Random and Deterministic Search Methods.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Informatica, 2007

The Criteria of Functional Delay Test Quality Assessment.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Transition Faults Testing Based on Functional Delay Tests.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Transition Fault Test Reuse.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

The Realization-Independent Testing Based on the Black Box Fault Models.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Informatica, 2005

Functional Test Generation Remote Tool.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2001

Procedures for Selection of Validation Vectors on the Algorithm Level.

Vacius Jusas, Kestutis Paulikas, Rimantas Seinauskas

Proceedings of the 2nd Latin American Test Workshop, 2001