Vacius Jusas

According to our database1, Vacius Jusas authored at least 39 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
An Ontology Based on the Timeline of Log2timeline and Psort Using Abstraction Approach in Digital Forensics.
Symmetry, 2020

An Abstraction Based Approach for Reconstruction of TimeLine in Digital Forensics.
Symmetry, 2020

The Phases Based Approach for Regeneration of Timeline in Digital Forensics.
Proceedings of the International Conference on INnovations in Intelligent SysTems and Applications, 2020

2019
Classification of Motor Imagery Using Combination of Feature Extraction and Reduction Methods for Brain-Computer Interface.
Inf. Technol. Control., 2019

Logical filter approach for early stage cyber-attack detection.
Comput. Sci. Inf. Syst., 2019

2018
Development of a Modular Board for EEG Signal Acquisition.
Sensors, 2018

Black box delay fault models for non-scan sequential circuits.
Comput. Sci. Inf. Syst., 2018

2017
Methods and Tools of Digital Triage in Forensic Context: Survey and Future Directions.
Symmetry, 2017

Application of Convolutional Neural Networks to Four-Class Motor Imagery Classification Problem.
Inf. Technol. Control., 2017

Methodology to investigate BitTorrent sync protocol.
Comput. Sci. Inf. Syst., 2017

Software Engineering Competence Remote Evaluation Process Model.
Balt. J. Mod. Comput., 2017

Convolutional Neural Networks for Four-Class Motor Imagery Data Classification.
Proceedings of the Intelligent Distributed Computing XI - Proceedings of the 11th International Symposium on Intelligent Distributed Computing, 2017

2016
A Methodology and Tool for Investigation of Artifacts Left by the BitTorrent Client.
Symmetry, 2016

2015
Investigation of Artifacts Left by BitTorrent Client on the Local Computer Operating under Windows 8.1.
Inf. Technol. Control., 2015

Path delay test generation at functional level.
IET Comput. Digit. Tech., 2015

Fast DCT algorithms for EEG data compression in embedded systems.
Comput. Sci. Inf. Syst., 2015

Comparison of Feature Extraction Methods for EEG BCI Classification.
Proceedings of the Information and Software Technologies - 21st International Conference, 2015

Energy Efficient Method for Motor Imagery Data Compression.
Proceedings of the Information and Software Technologies - 21st International Conference, 2015

2014
Stimuli generation framework for testing multiple processes in VHDL.
Inf. Technol. Control., 2014

Stimuli generator for testing processes in VHDL.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2013
Delay fault testing using partial multiple scan chains.
Microelectron. Reliab., 2013

Combining Software and Hardware Test Generation Methods to Verify VHDL Models.
Inf. Technol. Control., 2013

Data compression of EEG signals for artificial neural network classification.
Inf. Technol. Control., 2013

Functional delay test generation approach using a software prototype of the circuit.
Comput. Sci. Inf. Syst., 2013

Novel Method to Generate Tests for VHDL.
Proceedings of the Information and Software Technologies - 19th International Conference, 2013

EEG Dataset Reduction and Classification Using Wave Atom Transform.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2013, 2013

2012
Evaluation of testability enhancement using software prototype.
IET Comput. Digit. Tech., 2012

FSM Based Functional Test Generation Framework for VHDL.
Proceedings of the Information and Software Technologies - 18th International Conference, 2012

EEG Dataset Reduction and Feature Extraction Using Discrete Cosine Transform.
Proceedings of the Sixth UKSim/AMSS European Symposium on Computer Modeling and Simulation, 2012

2011
Functional fault models for non-scan sequential circuits.
Microelectron. Reliab., 2011

2009
Functional delay test generation based on software prototype.
Microelectron. Reliab., 2009

2008
Test generation at the algorithm-level for gate-level fault coverage.
Microelectron. Reliab., 2008

Development of Functional Delay Tests.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Functional Test Generation Based on Combined Random and Deterministic Search Methods.
Informatica, 2007

The Criteria of Functional Delay Test Quality Assessment.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Transition Faults Testing Based on Functional Delay Tests.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Transition Fault Test Reuse.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
The Realization-Independent Testing Based on the Black Box Fault Models.
Informatica, 2005

Functional Test Generation Remote Tool.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005


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