Varun Saxena
Orcid: 0000-0003-1732-0257
According to our database1,
Varun Saxena authored at least 7 papers
between 2022 and 2026.
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Bibliography
2026
Design of a 65-nm CMOS Neuromorphic Circuit for Sequential Alphanumeric Pattern Detection With Experimental Verification.
IEEE Trans. Very Large Scale Integr. Syst., June, 2026
MOSFET-Meminductor Emulator Circuit with Experimental Validation and Application in Adaptive Learning and Chua's Oscillator Circuit.
Circuits Syst. Signal Process., April, 2026
2025
A Memcapacitor Emulator Circuit Using a Single MO-OTA with Experimental Results and its Application in Neuromorphic and Mathematical Operations.
J. Circuits Syst. Comput., 2025
2024
Circuits Syst. Signal Process., January, 2024
Scalable Comput. Pract. Exp., 2024
2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022