Venkata Yaswanth Raparti

Orcid: 0000-0001-8763-4118

According to our database1, Venkata Yaswanth Raparti authored at least 10 papers between 2015 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2025
Zen-Attention: A Compiler Framework for Dynamic Attention Folding on AMD NPUs.
CoRR, August, 2025

2024
Weight Block Sparsity: Training, Compilation, and AI Engine Accelerators.
CoRR, 2024

2020
Approximate NoC and Memory Controller Architectures for GPGPU Accelerators.
IEEE Trans. Parallel Distributed Syst., 2020

2019
Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures.
IEEE Trans. Multi Scale Comput. Syst., 2018

DAPPER: Data Aware Approximate NoC for GPGPU Architectures.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

PARM: power supply noise aware resource management for NoC based multicore systems in the dark silicon era.
Proceedings of the 55th Annual Design Automation Conference, 2018

2016
Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015


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