Victor Demjanenko

According to our database, Victor Demjanenko authored at least 6 papers between 1990 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

RTP Payload Format for Tactical Secure Voice Cryptographic Interoperability Specification (TSVCIS) Codec.

Victor Demjanenko, John Punaro, David Satterlee

RFC, August, 2020

2017

RTP Payload Format for the Mixed Excitation Linear Prediction Enhanced (MELPe) Codec.

Victor Demjanenko, David Satterlee

RFC, March, 2017

1996

Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses.

Wen-jann Yang, Ramalingam Sridhar, Victor Demjanenko

Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

1992

A special-purpose content addressable memory chip for real-time image processing.

Yong-Chul Shin, Ramalingam Sridhar, Victor Demjanenko, Paul W. Palumbo, Sargur N. Srihari

IEEE J. Solid State Circuits, May, 1992

Postal Address Block Location in Real Time.

Paul W. Palumbo, Sargur N. Srihari, Jung Soh, Ramalingam Sridhar, Victor Demjanenko

Computer, 1992

1990

Adjacency algorithms for linear octree nodes.

Djaffer Ibaroudene, Victor Demjanenko, Raj Acharya

Image Vis. Comput., 1990