Ramalingam Sridhar

Affiliations:
  • University at Buffalo, USA


According to our database1, Ramalingam Sridhar authored at least 77 papers between 1992 and 2019.

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Bibliography

2019
Energy-efficient and reliable in-memory classifier for machine-learning applications.
IET Comput. Digit. Tech., 2019

An Energy Efficient In-Memory Computing Machine Learning Classifier Scheme.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018
Centralized Priority Management Allocation for Network-on-Chip Router.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

A Power Analysis of Cryptocurrency Mining: A Mobile Device Perspective.
Proceedings of the 16th Annual Conference on Privacy, Security and Trust, 2018

Modeling Context-Adaptive Energy-Aware Security in Mobile Devices.
Proceedings of the 43rd IEEE Conference on Local Computer Networks Workshops, 2018

Context-sec: Balancing Energy Consumption and Security of Mobile Devices.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

2017
A detailed look into power consumption of commodity 60 GHz devices.
Proceedings of the 18th IEEE International Symposium on A World of Wireless, 2017

2016
A fully parallel content addressable memory design using multi-bank structure.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A novel fault-tolerant router architecture for network-on-chip reconfiguration.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A high throughput router with a novel switch allocator for network on chip.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A high speed and low power content-addressable memory(CAM) using pipelined scheme.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014
Variation Aware Sleep Vector Selection in Dual V<sub>t</sub> Dynamic OR Circuits for Low Leakage Register File Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Bidirectional data verification for cloud storage.
J. Netw. Comput. Appl., 2014

2013
Energy modeling for mobile devices using performance counters.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Lightweight Reconfigurable Encryption Architecture for Moving Target Defense.
Proceedings of the 32th IEEE Military Communications Conference, 2013

Application-driven power efficient ALU design methodology for modern microprocessors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

User-adaptive energy-aware security for mobile devices.
Proceedings of the IEEE Conference on Communications and Network Security, 2013

2012
Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A cross-layer game for energy-efficient jamming detection in ad hoc networks.
Secur. Commun. Networks, 2012

Hybrid-cell register files design for improving NBTI reliability.
Microelectron. Reliab., 2012

How to Bypass Verified Boot Security in Chromium OS
CoRR, 2012

PGV: A Storage Enforcing Remote Verification Scheme.
Proceedings of the IEEE 31st Symposium on Reliable Distributed Systems, 2012

Variation-and-aging aware low power embedded SRAM for multimedia applications.
Proceedings of the IEEE 25th International SOC Conference, 2012

CD-PHY: Physical layer security in wireless networks through constellation diversity.
Proceedings of the 31st IEEE Military Communications Conference, 2012

2011
Leakage current, active power, and delay analysis of dynamic dual V<sub>t</sub> CMOS circuits under P-V-T fluctuations.
Microelectron. Reliab., 2011

Improving Reliability of Jamming Attack Detection in Ad hoc Networks.
Int. J. Commun. Networks Inf. Secur., 2011

PVT variations aware optimal sleep vector determination of dual VT domino OR circuits.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Low power tri-state register files design for modern out-of-order processors.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Novel adaptive keeper LBL technique for low power and high performance register files.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A Simple Cost-Effective Framework for iPhone Forensic Analysis.
Proceedings of the Digital Forensics and Cyber Crime, 2010

2009
Variation aware low power buffered interconnect design.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

iForensics: Forensic Analysis of Instant Messaging on Smart Phones.
Proceedings of the Digital Forensics and Cyber Crime - First International ICST Conference, 2009

Game Theoretic Modeling of Jamming Attacks in Ad hoc Networks.
Proceedings of the 18th International Conference on Computer Communications and Networks, 2009

XLSEC - A Distributed Cross-Layer Framework for Security in Wireless Sensor Networks.
Proceedings of the 6th IEEE Consumer Communications and Networking Conference, 2009

D-RNA: Towards a DDoS Resistant Network Architecture using Social Network Analysis.
Proceedings of the ISCA 22nd International Conference on Computer Applications in Industry and Engineering, 2009

2008
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.
J. Electron. Test., 2008

A low power and low area active clock deskewing technique for sub-90nm technologies.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2007
Robust 3GHz CMOS low noise amplifier adapted for RFID receivers.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Intra-die process parameter variation and leakage analysis of cache at the microarchitectural level.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Impact of Variability on Clock Skew in H-tree Clock Networks.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Toward Building a Multi-level Robust Intrusion Detection Architecture for Distributed Mobile Networks.
Proceedings of the 27th International Conference on Distributed Computing Systems Workshops (ICDCS 2007 Workshops), 2007

Security Solution For Data Integrity InWireless BioSensor Networks.
Proceedings of the 27th International Conference on Distributed Computing Systems Workshops (ICDCS 2007 Workshops), 2007

2006
Energy Conservation in Sensor Networks through Selective Node Activation.
Proceedings of the 2006 International Symposium on a World of Wireless, 2006

High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Leakage Reduction for Domino Circuits in Sub-65nm Technologies.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

SRAM Local Bit Line Access Failure Analyses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits.
J. Low Power Electron., 2005

Analysis of a hybrid key management solution for ad hoc networks.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2005

A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A High-Performance Router Design for VDSM NoCs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

DG-SRAM: a low leakage memory circuit.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A cross-layer based intrusion detection approach for wireless ad hoc networks.
Proceedings of the IEEE 2nd International Conference on Mobile Adhoc and Sensor Systems, 2005

RG-SRAM: A Low Gate Leakage Memory Design.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Security for Energy Constrained RFID System.
Proceedings of the Fourth IEEE Workshop on Automatic Identification Advanced Technologies (AutoID 2005), 2005

2004
System-on-Chip (SoC): Clocking and Synchronization Issues.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Leakage aware SER reduction technique for UDSM logic circuits.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2003
A robust header compression technique for wireless Ad hoc networks.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2003

1999
A data-driven micropipeline structure using DSDCVSL.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
Double Pass Transistor Logic for High Performance Wave Pipeline Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
Multi-attribute Lexicon Generation by Hyper-linked Embedded Access Structure.
Proceedings of the International Database Engineering and Applications Symposium, 1997

1996
Hardware Design Rule Checker Using a CAM Architecture.
VLSI Design, 1996

Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses.
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995
Conference Reports.
IEEE Des. Test Comput., 1995

A CMOS wave-pipelined image processor for real-time morphology .
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A local clocking approach for self-timed datapath designs.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
An active intelligent decision support system - Architecture and simulation.
Decis. Support Syst., 1994

Synchronization of Wave-Pipelined Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1992
AMEC - Asynchronous microprogram execution controller.
Microprocess. Microprogramming, 1992

Postal Address Block Location in Real Time.
Computer, 1992


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